Japanese Patent Application Publication No. 2008-135522 (hereinbelow referred to as Patent Literature 1) discloses an insulated gate type semiconductor device including an element region in which a MOS structure is provided, and a circumferential region on a periphery of the element region. A plurality of gate trenches is provided in the element region, and a gate insulating film and a gate electrode are provided within each gate trench. A p-type bottom-surface surrounding region (hereinbelow referred to as element-bottom-surface surrounding region) is provided in a range exposed on a bottom surface of each trench. The circumferential region has a plurality of trenches provided so as to surround the element region. A p-type bottom-surface surrounding region (hereinbelow referred to as outer circumferential bottom-surface surrounding region) is provided in a range exposed on a bottom surface of each trench in the circumferential region. When a MOSFET is turned off, a depletion layer extends in the element region from the element-bottom-surface surrounding regions to a drift region. Due to this, depletion of the drift region in the element region is enhanced. Further, in the circumferential region, the depletion layer extends within the drift region from the outer circumferential bottom-surface surrounding regions. Due to this, depletion of the drift region in the circumferential region is enhanced. Accordingly, a voltage resistance of the insulated gate type semiconductor device is thereby improved.